The term “flop,” or “flip-flop,” is generally used to describe or to refer to a clocked electronic circuit having two stable states, which is used to store a value. A flop generally comprises two latch circuits. Flip-flops have many and varied applications, and are widely used in digital circuits. One important use of flip-flops is to store bits of an instruction within an instruction pipeline of a central processing unit (CPU) or graphical processing unit (GPU).
In a conventional flip-flop electronic circuit, data is stored in cross-coupled inverters. A first, or “master” latch comprises a pass or transmission gate and a cross-coupled inverter. A second, or “slave” latch similarly comprises a pass gate and a cross-coupled inverter. A clock signal controls the operation of the two pass gates, and hence the operation of the flip-flop circuit.
Unfortunately, most flip-flops have a relatively low usage rate or duty cycle. For example, a given flip-flop may only change state on about ten percent or less of clock cycles. As numerous devices, e.g., portions of gates, including pass gates, receive such clock signals in a conventional flip-flop circuit, such devices dissipate clocking power with every clock signal transition. For complementary metal oxide semiconductors (CMOS) circuits, dynamic, or active power is given approximately by p=CV2f, where C is the active switching capacitance, V is the supply voltage, and f is the frequency of operation. All devices, e.g., field effect transistors (FETs), that receive a clock signal dissipate dynamic power due to the switching capacitance of the device. The total dynamic power due to clocking is proportional to the total switching capacitance. Since the flip-flop may be inactive for 90 percent or more of clock cycles, such clocking power consumed while the flip-flop is otherwise quiescent is unproductive, and wasted.
Such deleterious dissipation of active power due to quiescent clocking has many undesirable effects, including, for example, increasing total power consumption, which may decrease battery life, and increasing a temperature of an integrated circuit, which may require costly increased heat mitigation structures and techniques, e.g., heat sinks, and/or decrease reliability of the integrated circuit.